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SPI Master/Slave
Table 2.
SPI Registers
Mnemonic
Register Name
SPI_REV
Identification register
Reserved
Reserved
Reserved
SPI_SCR
System configuration register
SPI_SSR
System status register
SPI_ISR
Interrupt status register
SPI_IER
Interrupt enable register
Reserved
SPI_SET1
Set up 1 register
SPI_SET2
Set up 2 register
SPI_CTRL
Control register
SPI_DSR
Data status register
SPI_TX
Transmit register
SPI_RX
Receive register
SPI_TEST
Test register
Table 3.
Identification Register Bit Description (SPI_REV—0x000)
Bit
Name
31:8
Reserved
7:0
REV
20
Serial Interfaces
Base Address = 0xFFFB 0C00
Base Address = 0xFFFB 0C00, Offset = 0x00
Function
A read access returns 0.
Revision number
The 4-bit LSB indicates a minor revision.
The 4-bit MSB indicates a major revision.
→
Ex: 0x10
version 1.0.
A write to this register has no effect.
A reset has no effect on the value returned.
Size (Bits)
Access
32
R
32
R/W
32
R
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R
32
R/W
32
R
32
R/W
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Access
R
R
SPRU760B
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