Texas Instruments OMAP5912 Reference Manual page 377

OMAP3.2 DPLL
Table 5. Control Register
Bit Name
15 LS_DISABLE
14 IAI
13 IOB
12 TEST
22 Clocks
Base Address = 0xFFFE CF00, Offset = 0x00
Function
Level shifter disable:
0: Level shifter in transparent mode; all signals
between wrapper and DPLL core connected.
1: Level shifter in isolated mode; wrapper and
DPLL core disconnected. DPLL core power
supply turned off: no leakage current between
VDD and VDD_DPLL.
Power-on value is 0.
Initialize after idle:
Set high: DPLL starts entire locking sequence
after idle is deactivated.
Set low: DPLL attempts to lock using internal
delay chain setting before entering lock mode.
Power-on value is 0.
Bit no longer useful and must be set to 0.
Initialize on breako
When high: DPLL switches to bypass mode and
starts new locking sequence if DPLL core
indicates lock lost.
When low: DPLL continues ro putput
synthesized clock even if core indicates lock lost
but BREAKLN remains low.
Power-on value is 1.
Controls test output clock on TCLKOUT pin:
Test = 0: TCLKOUT = CLKOUT when in test
mode
Test = 1: TCLKOUT = CLKOUT/32 when in test
mode
Test = X: TCLKOUT = 0 when not in test mode
R/W Reset
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x0
SPRU751A