Texas Instruments OMAP5912 Reference Manual page 379

OMAP3.2 DPLL
Table 5. Control Register (Continued)
Bit Name
1 BREAKLN
0 LOCK
24 Clocks
Base Address = 0xFFFE CF00, Offset = 0x00
Function
Indicates break:
0: DPLL has broken lock for some reason.
1: Lock condition has been restored or write to
control register has occurred.
Indicates lock status:
0: DPLL in bypass mode and CLKOUT contains
divided-down output clock.
1: DPLL in Lock mode and CLKOUT is desired
synthesized clock frequency.
Because the dedicated VDD for the DPLL (VDD_DPLL) is either greater or
less than the VDD core, a collar is implemented to isolate the DPLL. This collar
includes level shifters that adapt the incoming control signals and the DPLL
outputs to the appropriate level (see Figure 4).
-
When enabled (LS_DISABLE = 0), the level shifter is seen as a buffer.
-
When disabled (LS_DISABLE=1), the level shifter is in isolated mode and
its output is grounded.
LS_DISABLE is a read/write control bit in the DPLL control register. Its re-
set value is 0.
R/W Reset
R 0x0
R 0x0
SPRU751A