Texas Instruments OMAP5912 Reference Manual page 152

Traffic Controller
Table 10. OCP-T1 and OCP-T2 Priority Time-Out Registers 2 (OCPT1_PTOR2 and
OCPT2_PTOR2) (Continued)
Bits Field
15:8 RESERVED
7:0 LCD
Table 11. OCP-T1 and OCP-T2 Priority Time-Out Registers 3 (OCPT1_PTOR3 and
OCPT2_PTOR3)
Bits Field
31:8 RESERVED
7:0 OCP-I
Table 12. OCP-T1 and OCP-T2 Abort Time-Out Registers (OCPT1_ATOR and
OCPT2_ATOR)
Bits Field
31:9 RESERVED
8 TIMEOUT_EN
7:0 TIMEOUT
94 OMAP3.2 Subsystem
Description
Reserved. To ensure software compatibility, reserved
bit should be written to 0 and read value should be
considered undefined.
Number of TC_CK cycles that LCD must wait in
low-priority queue before going to high-priority queue
Base Address = 0xFFFE CC00, Offsets = 0xA8 and 0xDC
Description
Reserved. To ensure software compatibility, reserved
bit should be written to 0 and read value should be
considered undefined.
Number of TC_CK cycles that OCP-I must wait in
low-priority queue before going to high-priority queue.
The priority time-out registers (OCPTx_PTORy) are used to store the number
of TC_CK clock cycles before DSP, DMA, LCD, or OCPI requests are made
high priority in the dynamic priority scheme for the OCP target.
Base Address = 0xFFFE CC00, Offsets = 0xAC and 0xE0
Description
Reserved. To ensure software compatibility, reserved
bit should be written to 0 and read value should be
considered undefined.
Enable time-out bit.
0: Disable
1: Enable
Number of counted-down clock cycles before
sending out abort signal if there is no response from
the slave.
R/W Reset
R/W 0x00
R/W 0x00
R/W Reset
R/W 0x000000
R/W 0x00
R/W Reset
R/W 0x000000
R/W 1
R/W 0xFF
SPRU749A