Texas Instruments OMAP5912 Reference Manual page 154

Traffic Controller
Table 14. OCP-T1 and OCP-T2 Abort Type Registers—Access Address
(OCPT1_ATYPER and OCPT2_ATYPER) (Continued)
Bits Field
2:1 HOST_ID
0 ABORT_FLAG
Table 15. OCP Target Configuration Register (OCPT_CONFIG_REG)
Bits Field
31:2 Reserved
1 PIPELN_RD_EN
0 AUTO_GATED_CLK
3.6 EMIFS Registers
Table 16. EMIFS Registers
Name
EMIFS_PRIOR
EMIFS_CONFIG
Note: The EMIFS chip-select configuration register reset values depend on the input boot pin state at IC reset release time.
For more details, see Section 3.2.18, EMIFS Boot Mode.
96 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offsets = 0xB4 and 0xE8
Description
Host ID of request that caused memory fault
00: MPU
01: DSP
10: DMA
11: OCPI
0: No abort
1: Abort
Base Address = 0xFFFE CC00, Offset = 0xB8
Description
Reserved, must be all 0s
0: Pipeline read operation disabled
1: Pipeline read operation enabled
0: Autogating clock disabled
1: Autogating clock feature enabled to save power
This register contains the PIPELN_RD_EN bit to enable or disable the pipeline
read operation in OCP Target. When enabled, the OCP target will start the
next read command when the accept for the previous read command arrives.
Table 16 lists the 32-bit EMIFS registers. Table 17 through Table 28 describe
the register bits.
Base Address = FFFE CC00
Description
EMIFS LRU priority register
EMIFS configuration register
R/W Reset
R 00
R 0
R/W Reset
R/W 0
R/W 1
R/W 0
R/W Offset
R/W 0x04
R/W 0x0C
SPRU749A