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Figure 10.
Basic Diagram of the ULPD Output and Input Clocks
MPU peripheral clock
ULPD_PLL_CLK
32 kHz clock
SYS_CLK_IN
SPRU753A
EXT_48M
Table 4 describes how clocks are gated by the ULPD. It shows:
-
The source of each clock output with its associated selection signal
-
The specific enable signal and clock request whenever the clock can be
gated
See Section 1.24 for more details on registers.
ULPD
Power Management
Ultralow-Power Device
CAM.EXCLK
System clock
48 MHz (UART1)
48 MHz (UART2)
48 MHz (UART3)
48 MHz (USB OTG)
12/13-19.2 Mhz
(to APLL)
Clock (Camera I/F)
MCLK
BCLK
SYS_CLK_OUT
12 MHz/ 32kHz
32 kHz (gated)
USB.CLKO
48 MHz (APLL)
48 MHz (MMCSDIO1)
48 MHz (MMCSDIO2)
System clock (FAC)
12/13-19.2 MHz
(gated/to OMAP3.2)
35
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