Texas Instruments OMAP5912 Reference Manual page 1117

SPI Master/Slave
1.4.4 Transmission Modes
Figure 15. Example of a Transmission With CPi = 0
CI = 0
SRCLK
CI = 1
CE = 1
1 * SRCLK
TSPENi
CE = 0
TSPDO
TSPDI
52 Serial Interfaces
The serial interface is active as soon as the shift register clock is activated.
nSPEN0 behaves the same as nTSPENi, as shown in Figure 15 and
Figure 16.
The transmitted data packet is shifted out on the rising or falling edge of
SRCLK, whereas the received data packet is captured on the falling or rising
edge of SRCLK (complementary edge).
When CPi = 0, the first edge (rising or falling) of SRCLK is used to capture the
data and the second edge (falling or rising) is used to shift the data.
1
MSB
MSB
When CPi = 1, the first edge (rising or falling) of SRCLK is used to shift the data
and the second edge (falling or rising) is used to capture the data.
NB
1 * SRCLK
LSB
LSB Q
SPRU760B