Texas Instruments OMAP5912 Reference Manual page 163

Table 29. EMIFF Registers
Name
EMIFF_PRIOR
EMIFF_CONFIG
EMIFF_MRS *
EMIFF_CONFIG2
EMIFF_DLL_WRD_CTRL
EMIFF_DLL_WRD_STAT
EMIFF_MRS_NEW *
EMIFF_EMRS0
EMIFF_EMRS1
EMIFF_OP
EMIFF_CMD
EMIFF_PTOR1
EMIFF_PTOR2
EMIFF_PTOR3
EMIFF_AADDR
EMIFF_ATYPER
EMIFF_DLL_LRD_STAT
EMIFF_DLL_URD_CTRL
EMIFF_DLL_URD_STAT
Note: EMIFF_MRS is a legacy register. Old software can use this register at offset 0x24. However, new software should use
the EMIFF_MRS_NEW register at 0x70.
SPRU749A
Base Address = 0xFFFE CC00
Description
EMIFF priority register
EMIFF configuration register
EMIFF SDRAM MRS register (legacy)
EMIFF configuration register 2
DLL WRD control register (write byte)
DLL WRD status register
EMIFF SDRAM MRS register (new)
EMIFF SDRAM EMRS0 register
EMIFF SDRAM EMRS1 register
EMIFF SDRAM operation register
EMIFF SDRAM manual command register
EMIFF dynamic arbitration priority time-out1
EMIFF dynamic arbitration priority time-out2
EMIFF dynamic arbitration priority time-out3
EMIFF abort address register
EMIFF abort type register
DLL LRD status register
DLL URD control register (read lower byte)
DLL URD status register (read upper byte)
Traffic Controller
R/W Offset
R/W 0x08
R/W 0x20
R/W 0x24
R/W 0x3C
R/W 0x64
R 0x68
R/W 0x70
R/W 0x74
R/W 0x78
R/W 0x80
R/W 0x84
R/W 0x8C
R/W 0x90
R/W 0x94
R 0x98
R 0x9C
R 0xBC
R/W 0xC0
R 0xC4
OMAP3.2 Subsystem 105