Texas Instruments OMAP5912 Reference Manual page 930

Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
Table 12. Control Register Bit Descriptions
Name Function
GLOBAL_MASK Setting this bit to 1 has the following effect (in this order):
Resetting this bit has the following effect (in this order):
This behavior is shown in Figure 3.
NEW_FIQ_AGR New FIQ agreement
Writing a 1 resets FIQ output and enables a new FIQ generation.
The FIQ output is reset if the corresponding bit of the ITR of the treated interrupt has
been cleared or masked.
Write access to this register bit is stalled until FIQ output is cleared. This bit is write only.
Reading it always returns 0.
NEW_IRQ_AGR New IRQ agreement
Writing a 1 resets IRQ output and enables a new IRQ generation.
The IRQ output is reset if the corresponding bit of ITR of the treated interrupt has been
cleared or masked.
Write access to this register bit is stalled until IRQ output is cleared. This bit is write
only. Reading it always returns 0.
Table 13. Interrupt Level Register (ILR)
@0x1C−
0x98
Access
Default
†
CODE_NB_IT = 7 for the MPU interrupt handler; CODE_NB_IT = 6 for the DSP interrupt handler.
32 Interrupts
All incoming or software generated (through SISR) interrupts are still stored in
ITR, but neither FIQ nor IRQ are.
When this bit is set and IRQ and FIQ are inactive and no IRQ/FIQ are to occur, the
IRQ_SECURE_MASK_N signal is asserted.
IRQ_SECURE_MASK_N signal is deasserted.
FIQ and IRQ generation become possible again (and all pending interrupts are
processed normally).
To allow for future evolution, when the software writes into this register all
reserved bits must be written as 0.
CODE_NB_IT+1 ... 2
PRIORITY
RW
0
† 1 0
SENS_ FIQ_nIRQ
nEDGE
RW RW
0 0
SPRU757B