Texas Instruments OMAP5912 Reference Manual page 246

Mailboxes
6.1.1 Mailbox Interrupts
188 OMAP3.2 Subsystem
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MPU2DSP1A and MPU2DSP1B for mailbox1
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MPU2DSP2A and MPU2DSP2B for mailbox2
The sequence is as follows:
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An interrupt for the DSP is generated when the MPU/DMA/OCP-I
writes to the second register; that is, MPU2DSP1B or MPU2DSP2B.
Writing to the first registers MPU2DSP1A or MPU2DSP2A does not
generate an interrupt.
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Once an interrupt has been set up, registers associated with this
mailbox interrupt are locked until DSP clears the interrupt flag by
reading the second register. For example, when MPU2DSP1B is
written by the MPU, the MPU can write to neither MPU2DSP1A or
MPU2DSP1B until the DSP clears the interrupt flag by reading
MPU2DSP1B.
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The DSP uses the following registers to communicate with the MPU:
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DSP2MPU1A and DSP2MPU1B for mailbox1
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DSP2MPU2A and DSP2MPU2B for mailbox2
Each mailbox interrupt is also associated to an interrupt flag bit (INT) which is
set to 1 when the interrupt is pending. The four flag registers are as follows:
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MPU flag registers:
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MPU2DSP1_FLAG
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MPU2DSP2_FLAG
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DSP flag registers:
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DSP2MPU1_FLAG
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DSP2MPU2_FLAG
These flag registers reflect only the state of the mailbox; a write into them has
no effect.
The interrupt flag register is set to 1 whenever a write is detected in the second
register of a mailbox. This interrupt flag is cleared whenever a read is detected
on the second data register, by the interrupted processor, of a mailbox interrupt
(see Section 6.2, Registers, for details).
When the interrupt flag has been set up by a processor, this processor can
write to neither of the registers associated with that mailbox interrupt until the
other processor cleans the interrupt flag.
SPRU749A