Texas Instruments OMAP5912 Reference Manual page 570

Ultralow-Power Device
Table 8. Counter 32 LSB Register (COUNTER_32_LSB_REG)
Bit Name
15:0 COUNTER_SLEEP_
CLK_LSB
Note: The CPU must check that the IT_STATUS_REG[0] bit has been asserted high before reading this register.
Table 9. Counter 32 MSB Register (COUNTER_32_MSB_REG)
Bit Name
15:4 RESERVED
3:0 COUNTER_32_MSB
Note: The CPU must check that the IT_STATUS_REG[0] bit has been asserted high before reading this register.
Table 10. Counter High-Frequency LSB Register
(COUNTER_HIGH_FREQ_LSB_REG)
Bit Name
15:0 COUNTER_HIGH_
FREQ_LSB
Note: The CPU must check that the IT_STATUS_REG[0] bit has been asserted high before reading this register.
Table 11. Counter High-Frequency MSB Register
(COUNTER_HIGH_FREQ_MSB_REG)
Bit Name
15:6 UNUSED
5:0 COUNTER_HIGH_
FREQ_MSB
Note: The CPU must check that the IT_STATUS_REG[0] bit has been asserted high before reading this register.
52 Power Management
Base Address = FFFE 0800, Offset = 0x00
Function
Lower value of the number of sleep clock cycles
during gauging time
Base Address = 0xFFFE 0800, Offset = 0x04
Function
Reserved
Upper value of the number of 32-kHz clock cycles
during gauging time
Base Address = 0xFFFE 0800, Offset = 0x08
Function
Lower value of the number of high-frequency clock
during gauging time
Base Address = 0xFFFE 0800, Offset = 0x0C
Function
Unused
Upper value of the number of high-frequency clock
during gauging time
R/W Reset
R 0x1
R/W Reset
R 0x0
R 0x0
R/W Reset
R 0x1
R/W Reset
R 0x0
R 0x0
SPRU753A