Texas Instruments OMAP5912 Reference Manual page 135

SPRU749A
It can support one 16-bit device or two 8-bit devices. The external interface
data bus width is always 16 bits.
The following devices are supported:
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Standard single-data-rate SDRAM
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Low-power single-data-rate SDRAM
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Mobile double-data-rate SDRAM
In terms of capacity and organization for the memory components that can be
attached, the EMIFF can handle:
-
1G-bit, 512M-bit, 256M-bit, 128M-bit, 64M-bit, and 16M-bit devices
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2-bank16M-bit devices, 2-bank or 4-bank 64M-bit devices, and 4-bank
only for any other capacity
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x8 (two devices) or x16 (single device) data bus configuration, except for
the 1G-bit device. The EMIFF only supports x16 1G-bit device (a single
device). The maximum external SDRAM configuration is 128M bytes.
The SDRAM_type field of the EMIFF interface SDRAM configuration register
must be used to specify the physical configuration of the devices.
The SDRAM type selection is the first action required from the software driver,
using the SDRAM_Type field of the EMIFF SDRAM operation register. Types
supported are regular SDR SDRAM, low-power SDRAM, and mobile DDR
SDRAM.
The SDRAM controller supports:
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The self-refresh mode (idle), auto refresh, and other operating modes
(HPHB, LPLB, and POM0 modes).
-
MRS command and extended MRS command for DDR SDRAM and
low-power SDRAM, sent via the SDRAM request manager.
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For SDR SDRAM, all burst sizes, between 1 and 32 consecutive accesses
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For DDR SDRAM, only bursts of 8.
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Two pipelined levels of request from the SDRAM request manager to
enable page interleave timing and reduce overhead cycles by the burst
interruption mechanism.
Traffic Controller
OMAP3.2 Subsystem 77