Texas Instruments OMAP5912 Reference Manual page 284

Figure 3. C55x DSP Architecture
Data read address buses bb, cb, db (3 x 16)
Data read address buses
BAB, CAB, DAB (3 x 24)
Program address bus PAB (24)
TMS320C55x DSP
Instruction buffer
queue
(64 x 8 bit)
Program
read
bus PB
32
Instruction decoder
controller
1st
instruction instruction
Data write buses EB, FB (2 x 16)
SPRU750A
Figure 3 shows the C55x DSP architecture.
Program
counter
48 bits
Ret
A
2nd
Program
address
generation
Status
registers
Program
flow
Pipeline
protection
unit
Interrupts
For details on CPU architecture and instruction set, see the following
documents:
-
TMS320C55x Technical Overview (SPRU393)
-
TMS320C55x DSP CPU Reference Guide (SPRU371)
TMS320C55x DSP CPU Overview
Auxiliary
registers
[0:7]
MAC
Data
registers
[0:3]
AC0 AC1 AC2 AC3
Coefficient
data
pointer
Smemory/
Xmemory
Ymemory
Cmemory
ALU 16-bit
DSP Subsystem
MAC
40-bit ALU
Shifter
Transition
registers
Bit
operations
21