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Table 115. Channel Status Registers (DMA_CSR0...DMA_CSR5)
Bit
Name
31:7
Reserved
6
SYNC
SPRU755B
Each channel has an interrupt control register DMA_CICR that specifies one
or more DMA controller events triggering an interrupt. If an event occurs and
its interrupt enable (IE) bit is 1, an interrupt request is sent to the DSP CPU
where it can be serviced or ignored. Each channel has its own interrupt line
to the CPU and one set of flags and enable bits in the CPU.
There are two classes of events that can generate interrupts:
Status events: For example, new frame start or end of block
-
Error events: For example, time-out condition or event drop
-
The bus-error interrupt also has a set of flag and enable bits in the CPU.
Each time an event occurs, if the corresponding interrupt enable bit is set, the
channel sends an interrupt to the processor. Simultaneously, the
corresponding status bit is set in DMA_CSR (DMA channel status register).
Note:
A status bit in DMA_CSR is not set if the corresponding interrupt enable bit
in the DMA_CICR equals 0.
Function
Synchronization event status bit. The DMA
controller updates synchronization to indicate
when the synchronization event for the channel
has occurred and when the synchronized channel
has been serviced:
0: The DMA controller has finished servicing the
previous access request.
1: The synchronization event has occurred.
Channel is waiting for synchronized DMA request
to be scheduled. In response to the event, the
synchronized channel submits an access request
to its source port.
If a synchronization event occurs again before the
DMA controller finishes servicing the previous
DMA request, an error has occurred and the DMA
controller disables the channel (see Section 4.15,
Dropped Synchronization Event). You can track
this type of error using the DROP_IE bit and the
DROP bit.
To select a synchronization event for a channel,
use the synchronization bits of DMA_CCR.
Direct Memory Access (DMA) Support
DSP DMA
Type
Reset
R
0
167
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