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Description
4.1.2
Software Interrupt
4.1.3
Latency
44
Interrupts
Each incoming interrupt can be masked individually by setting the
corresponding bit in DSP_MIR to 1.
One interrupt level register (DSP_ILR) is associated with each incoming
interrupt. The DSP_ILR sets whether the interrupt is to be edge-triggered or
level-sensitive and assigns it a priority level: 0 (the highest priority level), 1, ...
14, 15 (the lowest priority level). If several interrupts have the same priority
level assigned, they are serviced in a predefined order: IRQ_15, IRQ_14, ...,
IRQ_1, IRQ_0. The DSP_ITR also allows routing of each of the 16 interrupts
to either of the two DSP core input interrupts: FIQ or IRQ.
The IRQ or FIQ outputs can be reset by writing a 1 to the corresponding bit of
DSP_CONTROL_REG to enable new IRQ or FIQ generation. The writing also
clears DSP_SIR_IRQ or DSP_SIR_FIQ. The corresponding bit in DSP_ITR
must be cleared before writing to the DSP_CONTROL_REG.
The interrupt handler also provides a 16-bit software interrupt register
(DSP_SISR), which corresponds to the same 16-bit external interrupt lines.
Writing a 0 followed by a 1 to the targeted bit generates an interrupt if the
corresponding DSP_ILR is set to edge-sensitive; otherwise, no interrupt is
generated.
An external interrupt request and an internal software request are merged
before being sent to the interrupt handler to be serviced. The software interrupt
register is always read back with a 0. You can use this software interrupt
mechanism to simulate an external interrupt and test the corresponding
interrupt driver as long as the interrupt line is programmed as edge-sensitive.
The DSP interrupt handler resides on the 16-bit DSP private TI peripheral bus
(TIPB) and runs at half the frequency of the DSP clock. The latency from an
incoming interrupt to FIQ/IRQ generation depends on the number of interrupts
arriving at the same time. If there is only one, the latency is 5 clock cycles. If
more than one interrupt become active at the same time and are routed to the
same FIQ/IRQ, the latency can reach 3 + N*2 cycles, where N is the number
of incoming interrupts.
All interrupts for the DSP subsystem and OMAP subsystem are brought to the
OMAP subchip boundary to provide maximum flexibility for system integration.
SPRU757B
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