Texas Instruments OMAP5912 Reference Manual page 315

TIPB Bridge
Table 14. Wait States
4.2 Idle Control and Idle Status Registers
52 DSP Subsystem
-
Time-out[6:0]
This field specifies the number of cycles that can elapse before the TIPB
returns a bus error condition. The seven-bit field specifies the number of wait
states. The time-out period is determined as
Time-out = value of time out[6:0] + 2 measured in DSP subsystem master
clock cycles
The default value is 0x7f (127).
To conserve power, the DSP subsystem is capable of idling certain circuits.
The DSP CPU and peripherals contain several clock domains that can be
turned off individually to conserve power. The active/idle status of the various
domains is controlled by the idle control register. When the DSP software
executes the IDLE instruction, the clock domains are configured according to
the settings of the idle control register (ICR) (see Table 15). The current idle
domain status is reflected by the state of the idle status register (ISTR) (see
Table 16).
The idle domains are:
0 CPU
1 DMA
2 Cache
3 Peripherals
4 DPLL
Number of
Wait States Strobe Period
0 DSP clk/2
1 DSP clk/3
2 DSP clk/4
3 DSP clk/5
4 DSP clk/6
5 DSP clk/7
6 DSP clk/8
7 DSP clk/9
SPRU750A