Texas Instruments OMAP5912 Reference Manual page 316

Multimedia processor device overview and architecture

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Table 15. Idle Configuration Register (ICR)

Reserved (not connected)

Reserved idle domain

EMIF idle domain

DPLL idle domain

Peripherals idle domain

Cache idle domain

DMA idle domain

CPU idle domain

When the DSP subsystem comes out of IDLE, the ICR configuration is retained until modified by the CPU. The next

time an IDLE instruction is executed, the same domains enter the idle state.

The DSP DPLL is controlled by the MPU subsystem. When entering

low-power mode requiring DSP DPLL off, the DSP sets DPLL idle domain on,

followed by the MPU idling the DPLL source by writing the appropriate control

registers (see Chapters 4 and 5).

DSP Subsystem

Chapters

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