Texas Instruments OMAP5912 Reference Manual page 744

System DMA
Table 93. DMA LCD Source Frame Number B1 Register (DMA_LCD_SRC_FN_B1)
Bit Name
15:0
Table 94. DMA LCD Source Element Number B2 Register (DMA_LCD_SRC_EN_B2)
Bit Name
15:0
Table 95. DMA LCD Source Frame Number B2 Register (DMA_LCD_SRC_FN_B2)
Bit Name
15:0
Table 96. DMA LCD Logical Channel Control Register (DMA_LCD_LCH_CTRL)
Bit Name
15:4 RESERVED
3:0 LCH_TYPE
120 Direct Memory Access (DMA) Support
Base Address = 0xFFFE E300, Offset Address = 0xE4
Function
LCD channel source frame number for block 1
LCD channel source frame number for block 1
-
Number of frames within a block (unsigned) for the video RAM buffer 1.
The maximum frame number is 65535.
The size in bytes of the data block to transfer is:
data_block_in_bytes = DMA_LCD_SRC_FN_B1 x
Base Address = 0xFFFE E300, Offset Address = 0xE2
Function
LCD channel source element number for block 2
LCD channel source element number for block 2
-
Number of elements within a frame (unsigned) for the video RAM buffer 2.
The maximum element number is 65535.
Base Address = 0xFFFE E300, Offset Address = 0xE6
Function
LCD channel source frame number for block 2
LCD channel source frame number for block 2
-
Number of frames within a block (unsigned) for the video RAM buffer 2.
The maximum frame number is 65535. The size in bytes of the data block
to transfer is:
data_block_in_bytes = DMA_LCD_SRC_FN_B2 x
Base Address = 0xFFFE E300, Offset Address = 0xEA
Function
Reserved
Logical channel type.
DMA_LCD_SRC_EN_B1 x
DMA_LCD_CDSP[DATA_TYPE_B1]
DMA_LCD_SRC_EN_B2 x
DMA_LCD_CSDP[DATA_TYPE_B2]
R/W Reset
R/W ND
R/W Reset
R/W ND
R/W Reset
R/W ND
R/W Reset
R/W ND
R/W 0000
SPRU755B