Texas Instruments OMAP5912 Reference Manual page 427

Reset Architecture
Table 3. Global Resets
Reset Source
Cold External
reset PWRON_
RESET
External
RTC_ON_
NOFF
Warm External
reset MPU_RST
10 Initialization
Event Reset Description
Low on Reset LCD controller
PWRON_ System DMA
RESET MPU port interface
L3 OCP initiator
L4 controller L4 controller
Traffic controller
DSP MMU
MPU TIPB bridge and peripherals
Shared peripherals p
In RESET_MODE 1 sole reset source
for Class1 modules: boot ROM, ULPD,
OMAP5912 conf, sync counter. Sole
reset source for RTC.
Low on Reset LCD controller
RTC_ON_ System DMA
NOFF if RTC MPU port interface
split power L3 OCP initiator
set to 1 (bit 6 set to 1 (bit 6 L4 controller L4 controller
of RTC_ Traffic controller
CTRL_REG) DSP MMU
MPU TIPB bridge and peripherals
Shared peripherals
Reset source for Class 1 modules Reset source for Class 1 modules
boot ROM,ULPD, OMAP5912 conf,
sync counter in RESET_MODE 1.
In RESET_MODE 0, does not reset
RTC.
Low on Reset LCD controller
MPU_RST System DMA
MPU port interface
L3 OCP initiator
L4 controller
Traffic controller
DSP MMU DSP MMU
MPU TIPB bridge and peripherals
Shared peripherals
Class 2 and class 3 modules. SDRAM
refresh mode switched to self-refresh
if previously set to autorefresh state.
Not applicable in RESET_MODE 1.
p
Status Bit
POR (bit 5) MPU clock
reset status register
(ARM_SYSST)
EXT_RST (bit 4) MPU
clock reset status
register (ARM_SYSST)
GLOB_SWRST (bit1)
MPU clock reset status
register (ARM_SYSST)
POR (bit5 5) MPU clock
reset status register
(ARM_SYSST)
EXT_RST (bit 4) MPU
clock reset status
register (ARM_SYSST)
GLOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
EXT_RST (bit 4) MPU
clock reset status
register (ARM_SYSST)
GLOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
SPRU752B