Texas Instruments OMAP5912 Reference Manual page 578

Ultralow-Power Device
Table 27. Power Control Register (POWER_CTRL_REG) (Continued)
Bit Name
8 SOFT_LDO_SLEEP
7 LDO_CTRL_EN
6 LDO_STEADY
5 UNUSED
4 DEEP_SLEEP_TRANSITION_EN
3 SW_SHUTDOWN
2 SW_SHUTDOWN_RST
1 LOW_PWR_REQ
0 LOW_PWR_EN
60 Power Management
Base Address = 0xFFFE 0800, Offset = 0x50
Function
Control the sleep of the e-LDO that
supplies the DPLL 1=> LDO sleep
is forced to active state.
0=> LDO not in sleep (except in
deep sleep mode if
LDO_CTRL_EN=1)
0: The sleep of the LDO is fully
controlled by SOFT_LDO_SLEEP
bit.
1: The LDO is powered down in
deep sleep mode OR if
SOFT_LDO_SLEEP=1.
Stability of LDO output voltage
status
0: LDO output voltage not stable
1: LDO output voltage stable
Unused
1: Transition to deep sleep mode
allowed
0: Transition to deep sleep mode
forbidden
Software generation of
RST_HOST_OUT
0: RST_HOST_OUT forced to low
1: RST_HOST_OUT not forced to
low
Allow to deactivate the output
RST_HOST_OUT when at 1
Low-power software request.
0: Does not force the LOW_PWR
signal to active state
1: Forces LOW_PWR signal to
active state
0: Low-power feature is disabled.
1: Low-power feature is available.
R/W Reset
R/W 0x0
R/W 0x0
R Unknown
R 0x0
R/W 0x1
R/W 0x1
R/W 0x0
R/W 0x0
R/W 0x0
SPRU753A