Texas Instruments OMAP5912 Reference Manual page 176

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Table 50. DLL URD Control Register (EMIFF_DLL_URD_CTRL)(Continued)
Bit Field
15:8 Delay
7:4 Reserved
3 LOADDLL
2 DLLPHASE
1 ENADLL
0 Reserved
Table 51. DLL URD Status Register (EMIFF_DLL_URD_STAT)
Bit Field
31:16 Reserved
15:8 DLLCOUNT
7:3 Reserved
2 Lock
118 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0xC0
Description
8-bit delay to adjust the digitally controlled delay, to
be used when the DLL is disabled.
Range 0...225
One step represents a 26.3 ps ± 10.5 ps delay
adjustment
Must be all 0s
Allows loading the delay field value into the DLL
module, as the initial value for the tracking counter, or
to force a given delay.
0: No action.
1: The DLL is loaded with the delay value, if ENADLL
is 1. The DLL tracking engine is stalled.
Nominal digitally controlled delay selection. This bit
has no effect if DLL is disabled
0: 72 degrees (20% of the clock period)
1: 90 degrees (25% of the clock period)
0: DLL is disabled.
1: DLL is enabled.
Must be 0.
This register controls the DLL for the upper read byte.
Base Address = 0xFFFE CC00, Offset = 0xC4
Description
Must be all 0.
Current DLL counter value for monitoring/debug
(assumes control bit ENADLL is 1 in DLL control
register.
Must be all 0.
DLL lock status (future, not in the current design)
0: DLL is not locked.
1: DLL is properly locked.
R/W Reset
R/W 0x00
R 0x0
R/W 0
R/W 0
R/W 0
R 0
R/W Reset
R 0x0000
R 0x00
R 0x0
R 0
SPRU749A