Texas Instruments OMAP5912 Reference Manual page 226

MPU and MPUI Port
5.1.1 Access Request
5.1.2 Endian Conversion
168 OMAP3.2 Subsystem
to which the MPUI has exclusive access. The DSP is denied access to the
host-only RAM portion; however, both the MPUI and the DSP can access the
other part of the SARAM (shared-access RAM). All access available to the
MPUI in HOM remains available even if the DSP is in idle mode. The MPUI
does not have access to the DARAM in HOM. The DSP TIPB peripherals are
accessible only by MPUI in HOM.
In SAM, the entire MPUI port RAM and DSP peripherals are accessible by the
MPUI and DSP. If both the DSP and the MPUI are accessing the same memory
or peripheral at the same time, priority is given to the DSP. The access is
synchronized to the internal DSP clock. Note that SARAM and the DSP TIPB
peripherals can be accessed by the MPUI both in HOM and SAM. The DARAM
and the EMIF, however, can be accessed by the MPUI only in SAM.
HOM is more efficient than the SAM because no synchronization is involved.
However, the HOM depends on the host operating frequency, which is
normally slower than the internal DSP clock. The system software can switch
between HOM and SAM, or vice versa, if desired., and it is up to the software
to manage the system resources.
Section 5.1.1 through Section 5.1.7 describe the MPUI functions.
If the MPU, OCP-I, and system DMA request access to the DSP
memory/peripherals at the same time, the MPUI gives priority to one of the
three, based on the ACCESS_PRIORITY bits of (MPUI_CONTROL). The
programmable priority scheme must be configured during the system boot
process. When the MPUI initiates an MPUI port access, it must wait until the
access is completed before starting a new one. Pipelining is not supported by
the MPUI.
The MPUI supports 8-, 16-, or 32-bit access requests, even though the
interface from the MPUI to the MPUI port is a 16-bit interface. The MPUI, on
receiving the 32-bit access request from the MPU, OCP-I, or system DMA,
initiates two 16-bit MPUI accesses, one after the other, one with address X and
other with address X + 2. On a 32-bit read access, The MPUI packs the data
from the two transactions and sends a signal to the MPU/OCP-I/system DMA
once the second 16-bit read is completed.
Because the MPUI uses little endian ordering and the MPUI port uses big
endian ordering, there is an endianism conversion block between the MPUI
and the MPUI port. This endianism block converts data between the little and
SPRU749A