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Table 3.
CS1 and CS2 Configuration Register Reset Value
Bits
31
30
Field
PGWST
EN
Reset
0
0
Bits
15
14
13
Field
PGWST/WELEN
Reset
1
1
3.3
EMIFF Programming
3.3.1
Main Features
76
OMAP3.2 Subsystem
Note that the internal boot ROM may change the values of the MAD bit
depending on the execution path.
When BW = 0, the following CS0 and CS3 configuration is selected.
J
RDMODE=0
J
FCLKDIV=3
J
RDWST=15
J
WELEN =15
J
WRWST=15
J
RT=0
When BW = 1, the following CS0 and CS3 configuration is selected.
J
RDMODE=7
J
FCLKDIV=0
J
PGWST=0
J
WRWST=0
J
RDWST=0
J
RT=1
The CS1 and CS2 reset configuration registers are independent of the boot
input pins state.
29
28
27
26
PGWST
0
0
0
0
12
11
10
WRWST
1
1
1
1
When BM is 0, CS0 is activated in the 0000:0000−03FF:FFFF range and CS3
is activated in the 0C00:0000−0FFF:FFFF range. When BM is 1, CS3 is
activated in the 0000:0000−03FF:FFFF range and CS0 is activated in the
0C00:0000−0FFF:FFFF range.
The OMAP EMIFF is an SDRAM controller that manages all accesses by the
various initiators of an OMAP-based system.
25
24
23
22
BTWST
MAD
0
0
0
0
9
8
7
6
RDWST
1
1
1
1
21
20
19
18
BW
RDMODE
0
1
0
0
5
4
3
2
RT
FCLKDIV
1
1
1
0
SPRU749A
17
16
0
0
1
0
1
1
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