Texas Instruments OMAP5912 Reference Manual page 1022

Table 13. Watchdog Write Pending Register (WWPS) (Continued)
Bit Name
1 W_PEND_WCRR
0 W_PEND_WCLR
Table 14. Watchdog Start/Stop Register (WSPR)
Bit Name
31:0 WSPR_VALUE
SPRU759B
Base Address = 0xFFFE B000, Offset = 0x34
Function
When equal to one, a write is pending to the
WCRR register.
When equal to one, a write is pending to the
WCLR register.
This 32-bit register is accessible in 16-bit mode.
In write-posting mode, the software must read the pending write status bits
(watchdog write-posted status register bits [4:0]) to ensure that the following
write access is not discarded because of an ongoing write synchronization
process. These bits are automatically cleared by internal logic when the write
to the corresponding register is acknowledged.
Base Address = 0xFFFE B000, Offset = 0x48
Function
WSPR value switches on/off watchdog module
with specific protocol.
This 32-bit register is accessible in 16-bit mode.
The 32-bit watchdog (timer counter + prescaler counter) can be
started/stopped by accessing WSPR with a specific start/stop sequence. To
disable the 32-bit watchdog, follow this sequence:
Write 0x XXXX AAAA in WSPR.
-
Write 0x XXXX 5555 in WSPR.
-
To enable the 32-bit watchdog, follow this sequence:
Write 0x XXXX BBBB in WSPR
-
Write 0x XXXX 4444 in WSPR.
-
A read on this register (WSPR) returns the last data written in WSPR.
32-Bit Watchdog Timer General Overview
R/W
R
R
R/W
R/W
Reset
0
0
Reset
0x0000 0000
Timers 19