Texas Instruments OMAP5912 Reference Manual page 378

Table 5. Control Register (Continued)
Bit Name
11:7 PLL_MULT (4:0)
6:5 PLL_DEV (1:0)
4 PLL_ENABLE
3:2 BYPASS_DIV (1:0)
SPRU751A
Base Address = 0xFFFE CF00, Offset = 0x00
Function
DPLL multiple value:
00000: CLKOUT = CLKREF * 1
00001: CLKOUT = CLKREF * 1
00010: CLKOUT = CLKREF * 2
00011: CLKOUT = CLKREF * 3
11111: CLKOUT = CLKREF * 31
DPLL divide value:
00: CLKOUT = CLKREF
01: CLKOUT = CLKREF/2
10: CLKOUT = CLKREF/3
11: CLKOUT = CLKREF/4
Minimum CLKOUT frequency is 0.25 * CLKREF.
When PLL_MULT(4:0) = 0 or 1, CLKOUT is not
synthesized by the DPLL, but is simply a
divided-down version of CLKREF. Affects lock
mode only.
DPLL enable:
0: Switched DPLL to bypass mode
1: Requests DPLL to enter lock mode: DPLL
starts locking sequence and changes to DPLL
synthesized value after locking CLKOUT.
Determines CLKOUT frequency when in bypass
mode:
00: CLKOUT = CLKREF
01: CLKOUT = CLKREF/2
1X: CLKOUT = CLKREF/4
OMAP3.2 DPLL
R/W Reset
R/W 0x0
R/R 0x0
R/W 0x0
R/W 0x0
Clocks 23