Texas Instruments OMAP5912 Reference Manual page 1000

Table 16. Peripheral Access Time Calculations (Continued)
GDMA Accesses
GDMA GDMA
pipeline pipeline
(1)
latency latency(initial,
intermediate,
close)
GDMA From request
peripheral to 4*32-bit
latency read from
CCP FIFO
GDMA DMA
EMIFF read/write
latency from/to EMIFF
DSP Public Peripherals
DSP to 16 bits
McBSP read/write
access
DSP Private Peripherals
DSP to level 16 bits
2.1 interrupt read/write
handler
access
DSP_DMA Accesses
DSP_DMA 16 bits
to EMIFF read/write
access
† This latency value includes the following:
− Initial latency: from enable to 1st transaction
− Pipeline latency: from source to destination
− Close latency: from last acknowledge to release of the channel
− For the normal and dedicated P-channel case
‡ Page open: external SDRAM is a mobile DDR
§ 51 equivalent TC cycles = 19 TC cycles plus 16 CCP interface cycles
SPRU758A
On-Chip/Off-Chip Memory and Peripheral Access Latencies
Burst Read
First Data
510 51
§
† ‡ †
145 /170 14.5
‡
17
(2)
Single Read
Line
Fill
230
† †
/ 135 /1 13.5 /1 110
‡ ‡ ‡
60 6 0
400
75
130
‡
0
Peripheral Interconnects
Single Write
23 200 20
† † †
/10 11 / 100 /9 10
‡ ‡
10 0
80 400 80
15 90 18
† † †
/12 26 / 120 /1 24
‡
10
‡
24
† ‡
/9
† ‡
/22
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