Freeze Mode; Configuration Examples; Example Of Configuring And Enabling Two-Way Set-Associative Cache; Example Of Configuring And Enabling Direct Map With One Ramset - Texas Instruments OMAP5912 Reference Manual

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Freeze Mode

Example of Configuring and Enabling Direct Map With One ½ Ramset

DSP Subsystem

I-cache is enabled. The CAEN = 1 request to enable the I-cache is not

instantaneous, and latency can occur before the I-cache is truly enabled.

RTR1/2 can be changed to map ramsets to different locations anytime when

the I-cache is enabled. Again, note that the ramset must be used in conjunction

with the cache memory (two-way or direct).

On a write to CAFRZ = 1 in the DSP CPU ST3 register, the content in the

I-cache is locked. During freeze mode, any I-cache miss does not update the

I-cache. Data that has been cached before freeze is still accessible if there is

a cache hit.

Any I-cache miss during freeze mode is forwarded to the EMIF as a burst

request. Therefore, each single request to a frozen I-cache is serviced by one

complete EMIF burst cycle. For this reason, code profiling during freeze states

is recommended to achieve optimal performance and to limit the number of

1) Set the GCR to have the following settings:

a) Global enable = 0

b) Way presence = 1

c) Way number = 01

d) Streaming = 1

e) Others = Don't care

2) Set the NWCR to have the following settings:

a) Enable = 1

b) Way size = 011

c) Others = Don't care

3) Write 1 to CAEN bit in CPU ST3 register.

This sequence of operations configures a direct map ramset with one ½

ramset. A ramset configuration must be used in conjunction with a cache

two-way configuration.

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