Texas Instruments OMAP5912 Reference Manual page 164

Traffic Controller
Table 29. EMIFF Registers (Continued)
Name
EMIFF_EMRS2
EMIFF_DLL_LRD_CTRL
Note: EMIFF_MRS is a legacy register. Old software can use this register at offset 0x24. However, new software should use
the EMIFF_MRS_NEW register at 0x70.
Table 30. EMIFF Priority Register (EMIFF_PRIOR)
Bit Name
31:16 RESERVED
15:12 L3_OCP
11:8 DMA
7 RESERVED
6:4 DSP
3 RESERVED
2:0 MPU
Table 31. EMIFF SDRAM Configuration Register (EMIFF_CONFIG)
Bit Field
31:30 Reserved
29:28 LG SDRAM
Type
27 CLK
106 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00
Description
EMIFF SDRAM EMRS2 register
DLL LRD control register
Base Address = 0xFFFE CC00, Offset = 0x08
Function
Reserved
L3 OCP consecutive access
DMA consecutive access
Reserved
DSP consecutive access
Reserved
MPU consecutive access
The EMIFF priority register allows the EMIFF to give consecutive accesses to
a master when the master has been granted the EMIFF interface. The MPU
and DSP can have 0 to 7 consecutive accesses and the DMA and the Level3
OCP initiator can have 0 to 15 consecutive accesses, according to the content
of the corresponding bits.
Base Address = 0xFFFE CC00, Offset = 0x20
Description
Must be 00
Used to define the larger SDRAM memories (256MB). See
Table 32.
Disable SDRAM clock.
0: Enable the clock to the external SDRAM bank
1: Disable the clock to the external SDRAM bank
R/W Offset
R/W 0xC8
R/W 0xCC
R/W Reset
R 0x0000
R/W 0000
R/W 0000
R 0
R/W 000
R 0
R/W 000
R/W Reset
R 00
R/W 00
R/W 0
SPRU749A