Texas Instruments OMAP5912 Reference Manual page 191

4.3 Power-Saving Modes and Wake-Up Control
4.3.1 MPU Idle Control
SPRU749A
generate proper interrupts. This free-running clock for external LCD controller
can only be cut off when the external LCD controller is in idle state.
This section describes the following power-saving features:
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MPU idle control
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DSP idle control
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Traffic controller idle control
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System DMA idle control
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MPU TIPB bridge idle control
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External device power control
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DPLL idle control
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Chip idle mode/deep sleep mode
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Wake-up control
The OMAP 3.2 hardware engine can operate in several power-saving modes
that can reduce the operating current by stopping the clock signals of unused
(inactive) domains without losing any data on operational context. When the
idle state is entered, the MPU domain clocks are turned off according to the
orderly sequenced events. The clock gating cell design ensures that clocks
are properly stopped and restarted without parasitic pulses.
Activating the wait-for-interrupt MPU instruction initiates the MPU idle mode.
It stops the MPU internal clocks, and then the STANDBYWFI signal from MPU
megacell is asserted high, indicating that the MPU internal idle state is entered.
Before the idle mode is entered, you can stop the MPU internal timer clock, the
LCD clock, the external peripheral clock, and the timer/watchdog clock by
setting to 0 the corresponding bits of the ARM_IDLECT2 register, or you can
set the corresponding bits of ARM_IDLECT1 register so that these peripherals
automatically go to idle when the MPU goes to idle (except for the LCD).
When the timer/watchdog timer is configured as a watchdog, its clock
(CK_REF/14) is never shut down, regardless of the value of the
IDLWDT_ARM bit in the ARM_IDLECT1 register, or the EN_WDTCK bit in the
ARM_IDLECT2 register.
The idle command is forwarded to the MPU interrupt handler and the MPU
clock is stopped when the interrupt handler acknowledges this request
(nopending interrupts).
When the MPU internal clocks are stopped, the MPU domain clocks are
stopped if they were not already disabled using ARM_IDLECT2 before MPU
went to idle.
Clock Generation and Reset Management
OMAP3.2 Subsystem 133