Table of Contents
Advertisement
Memory Interfaces for the EMIFS
2.1.9
Read ID Operation
Figure 9.
Read ID Operation
For N.F.M.C greater
than 256 Megabits.
34
Memory Interfaces
read/program/erase) after the reset command is written. If the NFMC is
already in reset state, the flash memory command register does not accept a
new reset command. It is recommended, after a hardware reset, to start any
access to the NFMC by sending a reset command.
The flash core has a product identification code. To read this code, the
command 0x90 is used, followed by an address input of 00h. Depending on
the size of flash core, the code can be composed of either 2 or 4 bytes (for the
512M bits and 1G bit). Reading the NFMC sequentially outputs the NMFC
manufacturer byte, the NFMC code or ID byte (a unique byte that represents
the size of the NFMC), a reserved byte, and the multiplane byte, respectively.
By reading the ID of the NFMC, the software determines which features are
supported by the NFMC (see Table 12, Characteristics of Supported NFMCs).
The memory core remains in read ID operation unless a new command code
is sent.
Start read ID
Write 0x00000000, NND_ADDR_SRC
Write 0x90, NND_COMMAND
Read data, NND_ACCESS
Read data, NND_ACCESS
Read data, NND_ACCESS
Read data, NND_ACCESS
End read ID
Writing to this register, also sends
the address to the flash core.
Gets manufacturer byte
Gets ID byte
Gets byte (don't care)
Gets multiplane byte
SPRU756A
Advertisement
Chapters
Table of Contents
