Texas Instruments OMAP5912 Reference Manual page 705

Table 31. Autoinitialization Configuration Bits Summary for LCD Channel in
Compatible Mode
Auto_init Repeat
Hardwired 1 Hardwired 1
0 (Software) X (Software)
1 (Software) X (Software)
DMA Configuration Registers I/O Space
Table 32. LCD Channel Register Mapping for OMAP 3.2 Respectively OMAP 3.0/3.1
Compatible Modes
SPRU755B
End_prog
Hardwired 1
X (Software)
X (Software)
Each channel has its own address space. The configuration address is split
into several fields. Each field is decoded to generate a channel select and a
register select within the channel.
More configuration registers were added to the LCD channel OMAP 3.2. This
results in two different LCD channel register mappings which are dependent on the
mode selected, which is controlled by bit OMAP3_1_MAPPING_DISABLE in
register DMA_GSCR.
Table 32 shows the register mapping in the two different modes (OMAP
3.0/3.1 compatible or not).
Offset Register Mapping in OMAP 3.2
Mapping Mode
E3C0 DMA_LCD_CSDP
E3C2 DMA_LCD_CCR
E3C4 DMA_LCD_CTRL
E3C6 Reserved
E3C8 DMA_LCD_TOP_B1_L
E3CA DMA_LCD_TOP_B1_U
E3CC DMA_LCD_BOT_B1_L
E3CE DMA_LCD_BOT_B1_U
Autoinitialization Behavior
At the end of the current transfer, the logical LCD channel
immediately loads the physical LCD channel with its
programming register set, when physical LCD channel is
granted (end_prog = 1 allows loading the new context,
disregarding the repeat bit). The channel reinitializes itself
and starts a new transfer with the new context.
However, the LCD logical channel is active only when the
LCD controller enables it.
Not supported
Not supported
Direct Memory Access (DMA) Support
System DMA
Register Mapping in OMAP
3.0/3.1 Mapping Mode
DMA_LCD_CTRL
DMA_LCD_TOP_B1_L
DMA_LCD_TOP_B1_U
DMA_LCD_BOT_B1_L
DMA_LCD_BOT_B1_U
DMA_LCD_TOP_B2_L
DMA_LCD_TOP_B2_U
DMA_LCD_BOT_B2_L
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