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Table 74. DMA Logical Channel Configuration Registers (Continued)
Name
DMA_LCD_SRC_FN_B2
DMA_LCD_LCH_CTRL
†
Note: Some offsets are not in numerical order to facilitate the relationship between the upper and lower words of some regis-
ters.
Table 75. DMA LCD Channel Source Destination Parameters Register
(DMA_LCD_CSDP)
Bit
Name
15:14
BURST_EN_B2
13
PACK_EN_B2
12:11
DATA_TYPE_B2
10:9
RESERVED
8:7
BURST_EN_B1
6
PACK_EN_B1
5:2
RESERVED
1:0
DATA_TYPE_B1
SPRU755B
Base Address = FFFE EC00
Description
DMA LCD source frame number B2
DMA LCD logical channel control
Base Address = 0xFFFE E300, Offset Address = 0xC0
Function
Burst enable for block 2. (Tie off = 10)
Pack enable for block 2
Data type for block 2. (Tie off = 10)
Reserved
Burst enable for block 1. (Tie off = 10)
Pack enable for block 1
Reserved
Data type for block 1. (Tie off = 10)
The OMAP_3.1_mode tie-off values are the values given to the bits in
OMAP3.1 compatible mode, since the DMA_LCD_CCR, DMA_LCH_CTRL,
and DMA_LCD_CSDP registers do not exist in the compatible mode. These
values are tied off/on in hardware.
Used to control the LCD channel dual/single block transferring.
data_type_b1/data_type_b2: Defines the type of data moved in the LCD
-
channel from source port for block_1/block_2
DATA_TYPE [15:14] or [8:7]
00
01
10
11
R/W
R/W
R/W
s8: 8 bits scalar
s16: 16 bits scalar
s32: 32 bits scalar
illegal value
Direct Memory Access (DMA) Support
System DMA
†
Offset
0xE6
0xEA
R/W
Reset
R/W
00
R/W
0
R/W
00
R/W
ND
R/W
00
R/W
0
R/W
ND
R/W
00
type
109
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