Texas Instruments OMAP5912 Reference Manual page 926

Multimedia processor device overview and architecture
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Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
Table 6.
Interrupt Controller Registers (Continued)
Register
ILR10
ILR11
ILR12
ILR13
ILR14
ILR15
ILR16
ILR17
ILR18
ILR19
ILR20
ILR21
ILR22
ILR23
ILR24
ILR25
ILR26
ILR27
ILR28
ILR29
ILR30
28
Interrupts
Description
ILR Registers (Continued)
Interrupt priority level register bit 10
Interrupt priority level register bit 11
Interrupt priority level register bit 12
Interrupt priority level register bit 13
Interrupt priority level register bit 14
Interrupt priority level register bit 15
Interrupt priority level register bit 16
Interrupt priority level register bit 17
Interrupt priority level register bit 18
Interrupt priority level register bit 19
Interrupt priority level register bit 20
Interrupt priority level register bit 21
Interrupt priority level register bit 22
Interrupt priority level register bit 23
Interrupt priority level register bit 24
Interrupt priority level register bit 25
Interrupt priority level register bit 26
Interrupt priority level register bit 27
Interrupt priority level register bit 28
Interrupt priority level register bit 29
Interrupt priority level register bit 30
R/W
Offset
R/W
0x44
R/W
0x48
R/W
0x4C
R/W
0x50
R/W
0x54
R/W
0x58
R/W
0x5C
R/W
0x60
R/W
0x64
R/W
0x68
R/W
0x6C
R/W
0x70
R/W
0x74
R/W
0x78
R/W
0x7C
R/W
0x80
R/W
0x84
R/W
0x88
R/W
0x8C
R/W
0x90
R/W
0x94
SPRU757B

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