Texas Instruments OMAP5912 Reference Manual page 1090

Table 10. Control SPI Register Bit Description (SPI_CTRL—0x02C)
Bit Name
31:10 Reserved
9:7 AD
6:2 NB
1 WR
0 RD
Note: A write access to this register during a transaction does not affect the register and activates an OCP error.
Table 11. Shift Status Register Bit Description (SPI_DSR—0x030)
Bit Name
31:2 Reserved
1 TX_EMPTY
0 RX_FULL
SPRU760B
Base Address = 0xFFFB 0C00, Offset = 0x2C
Function
A read access returns 0.
Index of the addressed device
000: Enable device 0
001: Enable device 1
010: Enable device 2
011: Enable device 3
100: Enable device 4
Others: Undefined
Number of bits to receive/transmit
00000: 1 bit receive/transmit
11111: 32 bits receive/transmit
Write process activation− active high
Read and write process activation− active high
This register is dedicated to the activation of the serial port interface. It defines:
Read activation of the serial port
-
Write activation of the serial port
-
Number of bits to transfer (in the range 1 to 32)
-
External device address (up to 5)
-
Base Address = 0xFFFB 0C00, Offset = 0x30
Function
A read access returns 0.
Shift register is empty: Active high
This bit is cleared when the transmit register
(SPI_TX) has been written (in functional or
emulation mode).
Receive register is full: Active high
This bit is cleared when the receive register
(SPI_RX) has been read (not cleared from
debugger read).
SPI Master/Slave
Access Reset
R 0x000000
R/W 000
R/W 00000
R/W 0
R/W 0
Access Reset
R 0x0000000
R 1
R 0
Serial Interfaces 25