Texas Instruments OMAP5912 Reference Manual page 501

Multimedia processor device overview and architecture
Hide thumbs Also See for OMAP5912:
Table of Contents

Advertisement

Configuration
Table 48. Module Configuration Control 1 Register (MOD_CONF_CTRL_1)
(Continued)
Bit
Name
28
CONF_OSC1_GZ_R
27
CONF_OSC1_PWRDN_R
26
RESERVED
25
OCP_INTERCON_
GATE_EN_R
24
CONF_MMC2_CLKFB_
SEL_R
23
RESERVED
22
CONF_MCBSP3_CLK_
DIS_R
21
CONF_MCBSP2_CLK_
DIS_R
20
CONF_MCBSP1_CLK_
DIS_R
19:17
RESERVED
16
RESERVED
84
Initialization
Base Address = 0xFFFE 1000, Offset Address = 0x110
Function
Disables oscillator. See Table 49.
0: 12-MHz oscillator GZ pin is not activated.
1: 12-MHz oscillator GZ pin is activated
(oscillator is disabled).
See Table 49.
0: 12-MHz oscillator is not powered-down (uses
crystal).
1: 12-MHZ PWRDN pin is activated.
Reserved.
This bit enables the OCP interconnect to use its
autoidle feature on OCP interface.
This bit selects clock feedback into MMC/SDIO.
0: Output clock from MMC/SDIO is feedback.
1: Feedback comes from pad.
Reserved.
This bit enables the McBSP3 interface clock.
0: McBSP3 clock is enabled.
1: McBSP3 clock is disabled.
This bit enables the McBSP2 interface clock.
0: McBSP2 clock is enabled.
1: McBSP2 clock is disabled.
This bit enables the McBSP1 interface clock.
0: McBSP1 clock is enabled.
1: McBSP1 clock is disabled.
Reserved.
Reserved.
R/W
Reset
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x2
R/W
0x0 or
0x1
SPRU752B

Advertisement

Table of Contents
loading

Table of Contents