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SPI Master/Slave
Table 12. Transmit Register Bit Description (SPI_TX—0x034)
Bit
Name
31:0
SPI_TX
Notes:
1) The bits to transmit have to be aligned on the LSB of the SPI_TX register.
2) If the number of bits to transmit is 8, SPI_TX [7] is transmitted first, then SPI_TX [6], and so on.
3) If the number of bits to transmit is 32, SPI_TX [31] is transmitted first, then SPI_TX [30], and so on.
Figure 2.
Transmission Example
TSPDI
Note:
The number of bits of the word to be transmitted is programmed through NB bit field in the SPI_CTRL register. The trans-
mit register (SPI_TX) data loading must be completed according to the transmitted word bit length and in the proper se-
quence register access. SPI_TX register is considered as updated (transmit register full with new data) when the most-
significant byte part of the transmitted word has been written. If the number of bits of the transmitted word is not aligned on
a byte boundary, the value of the unused bits is considered as don't care.
-
0 ≤ NB ≤ 7: MSB = SPI_TX[7:0]
-
8 ≤ NB ≤ 15: MSB = SPI_TX[15:8]
-
16 ≤ NB ≤ 23: MSB = SPI_TX[23:16]
-
24 ≤ NB ≤ 31: MSB = SPI_TX[31:24]
The SPI_TX register is a 32-bit wide register that is 16-bit, or 32-bit addressable. Partial register update with successive
16-bit accesses can be used to load the transmit register. In that case, the LSB must be updated before the MSB part of
the transmitted word.
26
Serial Interfaces
The data to transmit are loaded to the SPI_TX register.
Base Address = 0xFFFB 0C00, Offset = 0x34
Function
Data to transmit
0
REG_TX
0
REG_SR
0
REG_RX
The received data are accessible on the OCP bus through SPI_RX register.
31
15
NB+1 bits
31
16
31
Access
Reset
R/W
0x00000000
TSPDO
SPRU760B
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