Texas Instruments OMAP5912 Reference Manual page 1057

Multimedia processor device overview and architecture
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32-kHz Synchronized Timer
54
Timers
The CR register is a read-only 32-bit register. Therefore, the MPU performs
a 32-bit access on the register while the DSP has to perform two consecutive
16-bit transactions.
In 16-bit mode, the following sequence must be followed to read the CR
register properly:
1) Read the lower 16 bits of the CR register (offset = 10).
2) When the CR is read and synchronized, the lower 16-bit LSB are read, and
the upper 16-bits of the CR MSB register are stored in a temporary
register.
3) Read the upper 16 bits of the CR register (offset = 12).
4) During this read, the value of the upper 16 bits that have been temporarily
stored is read.
Therefore, to read the value of CR correctly, the first read access must be to
the lower 16 bits (that is, offset = 10), followed by read access to the upper 16
bits (that is, offset = 12).
SPRU759B

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