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Level 1 MPU Interrupt Handler
3.1.3
Interrupt Sequence
Table 21. MPU Interrupt Sequence
Step
One or several
interrupts occur that set
the corresponding bits in
ITR
Processing the interrupt
Finish the interrupt
3.1.4
Interrupt Handler Software
3.1.5
Edge-Triggered Interrupts
38
Interrupts
Table 21 shows the MPU interrupt sequence for an IRQ interrupt only. The FIQ
interrupt sequence is identical.
Interrupt Handler Action
If one active interrupt occurs and the
IRQ is not already active, the interrupt
handler sends an IRQ.
If several active interrupts occur, the
interrupt handler must locate the
interrupt with the highest priority. If an
IRQ is not already active, the interrupt
handler sends an IRQ.
When the IRQ is sent, SIR_IRQ is
updated and the priority resolver is
reset.
To process edge-triggered and level-sensitive interrupts correctly, the
following sequences must occur in the system. Only the IRQ treatment is
described here. The FIQ treatment is exactly identical.
1) The interrupt handler module receives incoming one or more interrupts
from outside OMAP and registers it in the interrupt register (ITR).
2) If there are several active incoming interrupts, the interrupt handler
determines the highest priority interrupt and puts it in the N_IRQ register,
which is invisible to the software programmer.
MPU Action
The MPU must read SIR_IRQ to
determine the interrupt line being
serviced. Then the MPU runs the
corresponding subroutine.
1. The MPU must first clear the interrupt
bit in ITR (by writing a 0 in the
corresponding bit or by reading
SIR_IRQ.
2. For a level-sensitive interrupt, the
level must be removed from the source
that keeps the interrupt request low
(active) for the next interrupt to occur.
3. Sets
CONTROL_REG.NEW_IRQ_AGR to
reset IRQ output and SIR_IRQ, thus
allowing a new IRQ generation.
SPRU757B
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