Texas Instruments OMAP5912 Reference Manual page 133

3.2.18 EMIFS Boot Mode
SPRU749A
J
The abort flag bit is cleared when the abort type register is read.
J
At reset, TIMEOUT_EN is set to 1 and time-out value is set to 255
REF_CLK cycles.
There are a number of external mechanisms that affect the initial state of the
EMIFS during reset.
configuration (Table 18) and chip-select configuration (CS0 and CS3 only,
Table 19) registers changes depending on the state of these external
mechanisms. The three bits are BM (boot mode), BW (boot execution memory
width, either 16 or 32 bits), and MAD (multiplexed address and data protocol).
The reset value of these pins depends on the following:
BM reset value:
-
BM is 0 when:
J
MPU_BOOT is 0
OR
J
The device type is not emulation.
-
BM is 1 when:
J
MPU_BOOT (ball J20) is 1
AND
J
The device type is emulation.
BW reset value:
-
BW is 0 (boot execution is from 16−bit wide memory, external boot):
J
BM is 1.
-
BW is 1 (boot execution is from 32−bit wide memory, internal boot):
J
Device type is production type.
OR
J
The device type is emulation type AND MPU_BOOT is 0.
MAD reset value:
-
MAD is 0 (data and address non−multiplexed protocol):
J
Device type is production
OR
J
Device type is emulator AND either MPU_BOOT OR GPIO_1 is 0.
-
MAD is 1 (data and address multiplexed protocol):
J
Device type is emulation AND MPU_BOOT is 1 AND GPIO_1 is 1.
The reset value of three bit fields in the EMIFS
OMAP3.2 Subsystem
Traffic Controller
75