Texas Instruments OMAP5912 Reference Manual page 337

DSP Memory Management Unit
7.3.5 Table Walking Logic
74 DSP Subsystem
The entire TLB can be flushed at once by setting the global_flush bit in the
GFLUSH_REG register. TLB entries with a preserved bit set to 1 (bit P of the
CAM_L_REG register) are not flushed.
Regardless of the preserved bit setting, a specific TLB entry can be flushed
by setting the flush_entry bit in the FLUSH_ENTRY_REG register. The
specific entry to be flushed is specified by the logical address in the
CAM_H_REG and CAM_L_REG registers.
The 32 entries of the TLB may not be sufficient to store all the necessary
translations for all the memory space to be accessed. In this situation, a DSP
access generates a TLB miss when a logical address with no matching
translation is presented to the MMU. If the hardware table walker is disabled,
this miss generates an interrupt to the MPU while the DSP is held in a stalled
state. The MPU system software can update the TLB with the required
translation and release the DSP. A more efficient option is to enable the table
walker, as described in this section.
When the hardware table walker is enabled, it automatically fills the TLB when
misses occur. When a memory access is made and there is no TLB entry for
the logical address, the table walker loads the missing entry from the page
table stored in system (OMAP) memory (the MMU autonomously performs the
memory access and no intervention of the processor is required).
The OMAP memory area must be initialized with the level 1 and level 2 section
and page descriptors. The translation table base address, in the TTB_H_REG
and TTB_L_REG registers, must also be initialized with the (physical) address
of this OMAP memory area before enabling the MMU.
When a TLB miss occurs, a level 1 descriptor is read based on the logical
address and the value of TTB register, the read value gives information to the
MMU about the page (page size, protection, upper bits of the physical
address). If the page size read is not a section, but a coarse page or fine page
a second level descriptor is loaded. The level 1 descriptor address field and
the middle part of the logical address give the address where this level 2
descriptor is read. Once the value of this second level descriptor is read, the
MMU finally builds the TLB entry.
The TLB entry is written into one of the 32 TLB lines (CAM/RAM), replacing
a randomly chosen existing entry.
SPRU750A