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Layer 4 Interconnect
2.7.1
Reset Methodology
2.8
TIPB1-VIA/VIA-TIPB Wrapper
2.8.1
Reset Methodology
2.9
TIPB-OCP/OCP-TIPB Wrapper
2.9.1
Reset Methodology
2.9.2
DSP TIPB to OCP
32
Peripheral Interconnects
An MPU or a DSP initiator reset is always used internally by the static switch.
A reset on the static switch configuration register resets the DSP_SWITCH bit
and sets the MPU
SWITCH bit, which turns the static switch in the MPU
_
position.
The synchronous VIA protocol requires a free-running clock and synchronous
signals relative to this clock.
In addition to the TIPB bus signals, DMA requests need to be adapted.
Two successive DMA requests must be separated by at least two system DMA
clock cycles.
The internal state machine of the wrapper is reset by the MPU peripheral reset.
For the SoSSI peripheral, two resets must be provided to the peripheral:
-
L4_VIA_Reset: synchronous with the CK_DPLL1OUT
-
L4_DMA_Reset: synchronous with the DMA_LCDFREE_CLK
In both cases, the reset source is the MPU peripheral reset.
For the CCP peripheral, one reset is generated to the peripheral;
L4_VIA_RESET is synchronous with the ARMPER_CLK.
The synchronous OCP protocol requires a free-running clock and
synchronous signals realtive to this clock.
The free-running clock is ARMPER_CLK.
The NO_RESET signal comes from the wrapper to the connected peripheral.
This wrapper is sensitive to either DSP watchdog reset or DSP peripheral reset
in order to clear the interface state machine.
SPRU758A
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