Texas Instruments OMAP5912 Reference Manual page 689

Autoinitialization of Logical Channels
Table 27. Autoinitialization Configuration Bits Summary
Auto_init Repeat End_prog
Don't
0
care
1 0
1 0
1 1
OMAP3.0/3.1 System DMA Interrupt Mapping Rule
SPRU755B
In OMAP 3.0/3.1 compatible mode, autoinitialization is supported.
If a logical channel is autoinitialized, then the logical channel is automatically
enabled itself again when a transfer is ended. A new or old logical channel
configuration register set is loaded, and a new block of data is transferred.
Autoinitialization means that the logical channel gets reenabled. It does not
mean that the physical channel is kept for the logical channel. The logical
channel must return to the same scheduling schemes as normal before it gets
access to a physical channel.
The autoinitialization bit is used to set the DMA into autoinitialization mode
while END_PROG and REPEAT bits are used to control DMA behavior while
in autoinitialization mode. The bits AUTO_INIT, END_PROG, and REPEAT
are all located in the channel control register, DMA_CCR. Table 27
summarizes the autoinitialization mode.
Autoinitialization Behavior
No autoinitialization.
Don't care
Waits until software sets enable = 1 to enable the LCh and loads the PCh
with its programming register set.
As both repeat and end_prog bits equal 0, the LCh is still enabled, but
pending. At the end of the current transfer, the LCh channel waits until
repeat or end_prog = 1 to re-activate itself again.
0
When end_prog = 1, the programming register set is copied to the active
register set: a new context is programmed.
At the end of the current transfer, the LCh immediately loads the PCh with
its programming register set when PCh is granted (end_prog = 1 allows
1
loading the new LCh context, disregarding the repeat bit). The channel
reinitializes itself and starts a new transfer with the new context.
The LCh reinitializes itself at the end of the current transfer and starts a
Don't care
new transfer with the previous channel context (active register set).
This table differs slightly from what is implemented in OMAP 3.0/3.1 hardware,
where the programming register set is always loaded when END_PROG or
REPEAT is set to 1.
The OMAP 3.1 system DMA has nine channels plus one LCD channel, which
share seven interrupt lines; the OMAP 3.2 system DMA has one interrupt line
per channel. In order to be backward compatible, the below interrupt mapping
modes have been implemented.
Direct Memory Access (DMA) Support
System DMA
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