Texas Instruments OMAP5912 Reference Manual page 253

7.1.2 Access Permissions
7.1.3 TIPB Strobes and Access Factor
7.1.4 MPU Posted Write
SPRU749A
Access permissions to the MPU public and private TIPBs vary with initiator and
target. The MPU has unconditional access permissions to the MPU public and
private TIPBs.
The system DMA has unconditional access permission to the MPU public
TIPB and conditional, software-controlled access permission to the MPU
private TIPB. System DMA permission for the MPU private TIPB is
programmed in (ACCESS_CNTL).
The OCP-I has conditional, software-controlled access to both the MPU public
and private TIPBs. Refer to the Traffic Controller section for details on
programming OCP-I access permissions.
The TIPB strobes are an integral part of the TIPB bridge. The TIPB strobes are
(active low) signals output from the TIPB bridge module that drive the
peripheral interfaces of the MPU TIPB. The TIPB bridge uses two strobes
(strobe 0 and strobe 1), and each strobe is fixed to control access to distinct
ranges of the MPU TIPB peripherals address space. In addition, address
spaces defined to strobe 0 and strobe 1 are further segmented into areas of
MPU public TIPB and MPU private TIPB memory space. Refer to MPU
Peripherals Memory Mapping (see Chapter 10), for details on strobe address
space assignments.
The TIPB bridge may be required to communicate with peripherals of varying
speeds. To allow slow peripherals to answer, it is possible to lengthen the
strobe 0 and strobe
ACCESS_FACTOR1
ACCESS_FACTOR0 and ACCESS_FACTOR1 to n, the respective strobe
stretches its access over 2*n TIPB bridge clock cycles (n cycles the strobe is
inactive high; n cycles the strobe is active low).
The TIPB bridge clock referenced here is the input clock reference to the TIPB
bridge module generated from the clock and reset management module. The
clock rate for the TIPB bridge is fixed to the same value as that of the OMAP
3.2 traffic controller module. For details, see Chapter 4, Clock Generation and
Reset Management.
The MPU can perform a posted write. When posted write is enabled inside
(ARM_RHEA_CNTL), data sent by the MPU is buffered in the TIPB bridge
module, and the MPU can continue accessing other locations. The bridge
1 periods using
in (RHEA_CNTL).
OMAP3.2 Subsystem
TIPB Bridge
ACCESS_FACTOR0
By programming
and
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