Texas Instruments OMAP5912 Reference Manual page 787

Table 112. Channel Control Registers (DMA_CCR0...DMA_CCR5) (Continued)
Bit Name
7 EN
6 PRIO
SPRU755B
Function
Channel enable bit
Use EN to enable or disable transfers in the
channel. The DMA controller clears EN once a
block transfer in the channel is complete.
0: Channel is disabled. The channel cannot be
serviced by the DMA controller. If a DMA transfer
is already active in the channel , the DMA
controller stops the transfer and resets the
channel.
1: Channel is enabled. The channel can be
serviced by the DMA controller at the next
available time slot.
Clearing of this bit by the DMA because of block
completion has priority over a write by the DSP. If
both occur simultaneously, the DSP write is
discarded.
Note: Under certain conditions the DMA controller
can asynchronously reset the EN bit relative
to the DSP clock. Therefore, a metastable
condition can result if the DSP reads the bit
coincidentally with the DMA clear. In this
case the DSP might perceive the EN bit to be
set for an extra polling period.
Channel priority bit
All six DMA channels are given a fixed position
and programmable priority level on the service
chain of the DMA controller. PRIO determines
whether the associated channel has a high priority
or a low priority. High-priority channels are
serviced before low-priority channels.
0: The channel has the low-priority level.
1: The channel has the high-priority level.
Direct Memory Access (DMA) Support
DSP DMA
Type Reset
0 RW
0 RW
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