Texas Instruments OMAP5912 Reference Manual page 855

SPRU756A
for the last time. To finish the programming of the NFMC, the command 0x10
must be sent.
-
DMA writes the data in the FIFO: Once the FIFO is full, any access is
stalled.
-
When the FIFO is full, the internal counter is decremented, and the NFC
sends the data from the FIFO to the NFMC.
-
When the FIFO is empty, the DMA request is asserted low.
-
When the FIFO is empty and the counter is not zero, the DMA writes a new
batch of data in the FIFO.
-
If the counter is 0, the NFC sends the data from the FIFO to the NFMC for
the last time and the postwrite mechanism is stopped. No DMA request
is asserted.
While the FIFO is being filled, access to command, data, and address registers
is stalled.
When postwrite goes from 0 to 1:
-
The DMA request is asserted low.
-
The FIFO is flushed.
-
The internal counter is loaded with the BLOCK_COUNT value of the
NND_FIFOCTRL register.
When the postwrite goes from 1 to 0:
-
The next postwrite is aborted.
-
The DMA request is asserted to high.
Memory Interfaces for the EMIFS
Memory Interfaces 49