Texas Instruments OMAP5912 Reference Manual page 429

Reset Architecture
Table 3. Global Resets (Continued)
Reset Source
Warm Global
reset
system reset
(software)
(continued)
MPU WD
reset
DSP WD DSP WD
reset timeout
MPU Software
software
reset
MPU Software
peripheral
reset
12 Initialization
Event Reset Description
SW_RST Reset LCD controller
(bit 3) in System DMA
ARM_ MPU port interface
RSTCT1 is L3 OCP initiator
set to 1 or set L4 controller
ARM_RST Traffic controller
(bit 0) in DSP MMU
ARM_RSTC1 MPU TIPB bridge and peripherals
and clear Shared peripherals
DSP_EN (bit
SDRAM refresh mode switched to
1) in
self-refresh if previously set to
ARM_RSTC1
autorefresh state.
Class 2 and class 3 modules.
MPU WD Reset LCD controller
underflow System DMA
MPU port interface
L3 OCP initiator
L4 controller
Traffic controller
DSP MMU DSP MMU
MPU TIPB bridge and peripherals
Shared peripherals
SDRAM refresh mode switched to
self-refresh if previously set to
autorefresh state.
Class 2 and class 3 modules.
DSP WD Reset DSP system and peripheral
Underflow modules wrapper switches.
Reset WD_PER_EN (bit 1) in
DSP_RSTCT2.
ARM_RST Reset the MPU.
(bit 0) in
ARM_RSTC1
is set to 1
PER_EN Reset peripheral class 2 modules and
(bit 0) in peripheral modules wrapper switches.
ARM_RSTC2
is cleared to
0.
Status Bit
GLOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
ARM_WDRST (bit 2) in
MPU clock reset status
register (ARM_SYSST)
GLOB_SWRST (bit 1)
MPU clock reset status
register (ARM_SYSST)
DSP_WDRST (bit 0) in
MPU clock reset status
register (ARM_SYSST)
ARM_MCRST (bit 3) in
MPU clock reset status
register (ARM_SYSST)
SPRU752B