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Figure 13.
LCD Dual-Block Mode Transfer Scheme
3.2.8
LCD Channel OMAP 3.0/3.1 Compatible Mode Programming
Configuration Registers
Addressing Mode
SPRU755B
Frame buffer
Video frame 1
Video frame 2
DMA_LCD_CTRL [4] = BLOCK_2_IT_COND = 1: end of block 2 is
reached. The DMA restarts at the top address of block 1, and
DMA_LCD_CTRL [4] is reset to be able to detect a next interrupt.
Switching between the two frames is automatic; it does not need any
reconfiguration of the channel.
Users have the option of having new LCD channel features and maintaining
compatibility with the previous LCD channel. To keep compatible with the
OMAP3.1 programming mode, care must be taken on the following points.
Everywhere else, there is no compatibility obstacle.
The DMA_LCD_CTRL register is one of the LCD configuration registers. This
register manages the operation of dual or single block mode, the interrupt
enable bits, and the source port for the next transfer. Then it returns
information by setting the status bits in its register. An interrupt can be sent at
the end of the transfer of each block; this interrupt line is connected to the LCD
interrupt line of the DMA.
In OMAP 3.1 compatible mode, the LCD channel only supports the
post-increment addressing mode on the source side.
Address is post-incremented by element size (ES_B1 or ES_B2 depend-
ing on which block is active if in dual-block mode)
0x0B 0000
0x0B 00DE
DMA
0x0C 0000
0x0C 00DE
Direct Memory Access (DMA) Support
System DMA
LCD
controller
79
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