Summary of Contents for Texas Instruments OMAP5910
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OMAP5910 Dual-Core Processor MicroWire Interface Reference Guide Literature Number: SPRU686 October 2003...
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40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the OMAP5910 device and related peripherals. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
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Trademarks Related Documentation From Texas Instruments / Trademarks OMAP5910 Dual-Core Processor Universal Serial Bus (USB) and Frame Adjustment Counter (FAC) Reference Guide (literature number SPRU677) OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (literature number SPRU678) OMAP5910 Dual-Core Processor General-Purpose Input/Output (GPIO)
MicroWire Interface MicroWire Interface This serial synchronous interface can drive two serial external components. For the external devices, this interface is compatible with the MicroWire standard and is seen as the master (see Figure 1). A transmit DMA mode is available. Figure 1.
MicroWire Interface Table 4. Control-and-Status Register (CSR) Reset Value Bits Field Value Description RDRB RDRB bit = 1 indicates that the receive (RDR) area is full. When the controller reads the content of the RDR, this bit is cleared. This bit is read only. CSRB CSRB bit = 0 indicates that the control and status register (CSR) is ready to receive new data.
MicroWire Interface Table 4. Control-and-Status Register (CSR) (Continued) Reset Value Bits Field Value Description 9−5 NB_BITS_WR Number of bits to transmit Undefined 4−0 NB_BITS_RD Number of bits to receive Undefined This register sets up the serial interface for the first and the second external components.
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MicroWire Interface Table 5. Setup Register 1 (SR1) (Continued) Reset Value Bits Field Value Description CS0_EDGE_WR When the CS0 is selected, this bit defines the active Undefined edge of the serial clock, SCLK, used to write data to the serial input D0. (Output data is generated on this edge) Falling (the serial clock is not inverted) Rising (when the serial clock is inverted) Rising (the serial clock is not inverted)
MicroWire Interface Table 6. Setup Register 2 (SR2) Reset Value Bits Field Value Description CS3_CHK Before activating a write process, determines Undefined if the external device is ready. No check is done and the write process is immediately executed. If the DI signal is low, the interface considers the external component busy;...
MicroWire Interface Table 6. Setup Register 2 (SR2) Reset Value Bits Field Value Description CS3_EDGE_RD When the CS3 is selected, this bit defines the Undefined active edge of the serial clock, SCLK, used to read data from the serial input DI. (Input data is strobed on this edge) Falling (the serial clock is not inverted) Rising (when the serial clock is inverted)
MicroWire Interface This register sets up the serial-clock polarity. Table 8. Setup Register 4 (SR4) (Read/Write) Reset Value Bits Field Value Description CLK_IN The serial clock is not inverted The serial clock is inverted Note: Content of this register must not be changed when a read or write process is running. Table 9.
MicroWire Interface Table 9. Setup Register 5 (SR5) (Read/Write) Reset Value Bits Field Value Description IT_EN In the IT mode, an interrupt is generated each time a word has been transferred or received. This interrupt is a negative edge-triggered interrupt. A status register (IST) allows the CPU to know which interrupt (receive or/and transmit) occurred.
MicroWire Interface After the loading of the transmit data register (TDR), a write process is activated by setting the START bit to 1 and by writing a value different from zero to the NB_BITS_WR field. A read process is always simultaneous with a write process, which means that at every serial clock, SCLK, cycle data is read.
MicroWire Interface On the DI line, data is generated from the EEPROM interface on the SCLK rising edge and read by the MicroWire interface on the SCLK rising edge. Example of Protocol Using a Serial EEPROM (XL93LC66) Set up the interface by writing the following values in setup register 1 (SR1): CS_EDGE_RD = 1 CS_EDGE_WR = 0 CSCS_LVL = 1...
MicroWire Interface 8) Set the following fields of the control and status register (CSR): NB_BITS_RD: 16 (decimal) NB_BITS_WR: 0 (decimal) INDEX: 00 CS_CMD: 1 START: 1 Go to 5. 9) Set the following fields of the control and status register (CSR): INDEX: 00 CS_CMD: 0 START: 0...
MicroWire Interface 7) Set the following fields of the control and status register (CSR): NB_BITS_RD: 0 NB_BITS_WR: 16 (decimal) INDEX: 00 CS_CMD 1 START: 1 8) Wait for the CSRB bit of the CSR to be reset. 9) Set the following fields of the control and status register (CSR): INDEX: 00 CS_CMD: 0 START: 0...
MicroWire Interface 5) Wait for the CSRB bit of the control and status register (CSR) to be reset. 6) Load the transmit data register (TDR) with: D7d3...D0d3 D7d4...D0d4 D7d3...D0d3: Data for digit 3 D7d4...D0d4: Data for digit 4 7) Set the following fields of the control and status register (CSR): NB_BITS_RD: 0 NB_BITS_WR: 16 (decimal) INDEX: 01...
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MicroWire Interface 1) SR5 = DMA_TX_EN: 0 IT_EN: 1 AUTO_TX_EN: 1 CS_TOGGLE_TX_EN: 1 2) SR1 = CS0_EDGE_RD: 0 CS0_EDGE_WR: 1 CS0CS_LVL: 0 CS0_FREQ: 00 CS0_CHK: 1 Note: The data out is latched on the falling edge of the serial clock. The data in is sampled on the rising edge.
MicroWire Interface 11) Release the autotransmit mode: SR5 = AUTO_TX_EN: 0. 12) END The corresponding behavior of the serial interface is described in Figure 4. Figure 4. Read Cycle in the Autotransmit Mode WIRE_NCS UWIRE_SCCLK UWIRE_SDO UWIRE_SDI Example of the Autotransmit Mode With DMA Support The autotransmit mode and DMA mode are controlled by the setup register 5 (SR5).
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MicroWire Interface 6) When the DMA transfer is complete, check the status of the CSRB to find whether or not the MicroWire has finished the serial data transfer. 7) Write to the setup register (SR5) to disable DMA and AUTO TX mode: DMA_TX_EN = 0 IT_EN = 0 AUTO_TX_EN = 0...