Texas Instruments OMAP5912 Reference Manual page 935

Figure 4. MPU Interrupt Handler
Control register (CONTROL_REG)
TIPB
SPRU757B
Interrupt set register (SIR)
OR
Edge detection FLIP_FLOPS
Level or edge detected
Interrupt input register (ITR)
Mask interrupt register (MIR)
Interrupt level register 0 (ILR0)
Interrupt level register 1 (ILR1)
Interrupt level register 31 (ILR31)
SIR_IRQ
Interrupt encoded source register
SIR_FIQ
Interrupt encoded source register
itmr: ITR gated with MIR, to generate active interrupts
Level 1 MPU Interrupt Handler
32 external interrupts
itmr
Process next pending IRQ
Process next pending FIQ
Generate IRQ
Generate FIQ
IRQ
To MPU
Interrupts
FIQ
37