Texas Instruments OMAP5912 Reference Manual page 566

Ultralow-Power Device
Figure 16. RST_HOST_OUT Activation on PWRON_RESET
PWRON_RESET
RST_HOST_OUT
Figure 17. RST_HOST_OUT Activation on BFAIL/EXTFIQ and SW_SHUTDOWN
BFAIL/EXTFIQ
RST_HOST_OUT
SW_SHUTDOWN
SW_SHUTDOWN_RST
48 Power Management
2 x 32 kHz
clock cycle
Upon a low level on BFAIL/EXTFIQ input, which signals a battery fail event,
the ULPD starts a programmable counter. When the counter underflows,
ULPD asserts low RST_HOST_OUT and places OMAP3.2 in power-down
mode.
The delay from the falling edge of BFAIL/EXTFIQ to the falling edge of
RST_HOST_OUT is software programmable (see Table 21). The default
value is one CLK32K cycle. The release of the shutdown signal is also
controlled by software (see Table 28).
Programmable
delay
1 x 32kHz_CLK
Cycle required
minute required
It is also possible to use SW_SHUTDOWN (bit [3] of POWER_CTRL_REG)
to force low RST_HOST_OUT.
Note:
What is shown in Figure 17 as programmable delay corresponds to the
counter start time (three 32-kHz cycles) plus the counter decrement to 0. The
counter initial value corresponds to COUNTER_32_FIQ_REG.
1 x System Clock + 32-kHz
synchronization
1 x System clock cycle +
1 x 32-kHz_CLK cycle
SPRU753A